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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core, 1 kB 3 V flash with 128-byte RAM
Rev. 05 -- 28 September 2007 Product data sheet
1. General description
The P89LPC912/913/914 are single-chip microcontrollers in low-cost 14-pin packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC912/913/914 in order to reduce component count, board space, and system cost.
2. Features
2.1 Principal features
I 1 kB byte-erasable flash code memory organized into 256 B sectors and 16 B pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage. I 128 B RAM data memory. I Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow or to become a PWM output. I 23-bit system timer that can also be used as a RTC. I Two analog comparators with selectable inputs and reference source. I Enhanced UART with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities (P89LPC913, P89LPC914). I SPI communication port. I Internal RC oscillator (factory calibrated to 1 %) option allows operation without external oscillator components. The RC oscillator option is selectable and fine tunable. I 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V). I Up to 12 I/O pins when using internal oscillator and reset options.
2.2 Additional features
I 14-pin TSSOP packages. I A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz (167 ns to 333 ns at 12 MHz). This is six times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI. I In-Application Programming (IAP-Lite) and byte erase allows code memory to be used for non-volatile data storage.
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
I Serial flash In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. I Watchdog timer with separate on-chip oscillator, requiring no external components. The watchdog prescaler is selectable from eight values. I Low voltage reset (brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt. I Idle and two different power-down reduced power modes. Improved wake-up from Power-down mode (a LOW interrupt input starts execution). Typical power-down current is 1 A (total power-down with voltage comparators disabled). I Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available. I Configurable on-chip oscillator with frequency range options selected by user programmed flash configuration bits. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz (P89LPC912, P89LPC913). I Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function. I Programmable port output configuration options: quasi-bidirectional, open-drain, push-pull, input-only. I Port `input pattern match' detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern. I LED drive capability (20 mA) on all port pins. A maximum limit is specified for the entire chip. I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. I Only power and ground connections are required to operate the P89LPC912/913/914 when internal reset option is selected. I Four interrupt priority levels. I Four keypad interrupt inputs. I Second data pointer. I Schmitt trigger port inputs. I Emulation support.
P89LPC912_913_914_5
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Product data sheet
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8-bit microcontrollers with two-clock 80C51 core
3. Product comparison
Table 1 highlights the differences between these three devices. For a complete list of device features, please see Section 2 "Features" on page 1.
Table 1. Product comparison External X2 CLKOUT crystal pins X X X X T0 PWM output X X SPI with SS pin X X SPI without SS pin X UART TXD X X RXD X X Max fosc (MHz) 18 18 12
Type number
P89LPC912 P89LPC913 P89LPC914
4. Ordering information
Table 2. Ordering information Package Name P89LPC912FDH P89LPC912HDH P89LPC913FDH P89LPC914FDH TSSOP14 Description plastic thin shrink small outline package; 14 leads; body width 4.4 mm Version SOT402-1 Type number
4.1 Ordering options
Table 3. Ordering options Temperature range -40 C to +85 C -40 C to +125 C -40 C to +85 C -40 C to +85 C Frequency 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 18 MHz 0 MHz to 12 MHz Type number P89LPC912FDH P89LPC912HDH P89LPC913FDH P89LPC914FDH
P89LPC912_913_914_5
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Product data sheet
Rev. 05 -- 28 September 2007
3 of 66
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
5. Block diagram
P89LPC912
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
1 kB CODE FLASH internal bus
SPI
SPICLK MOSI MISO SS
128 BYTE DATA RAM
REAL TIME CLOCK/ SYSTEM TIMER
P3[1:0]
PORT 3 CONFIGURABLE I/O
TIMER 0 TIMER 1
T0
P2[5:2]
PORT 2 CONFIGURABLE I/O
CMP1 ANALOG COMPARATORS CIN2A CIN1A CMPREF
P1.2, P1.5
PORT 1 CONFIGURABLE I/O
P0.2, P0[6:4]
PORT 0 CONFIGURABLE I/O
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
KEYPAD INTERRUPT
WATCHDOG TIMER AND OSCILLATOR
PROGRAMMABLE OSCILLATOR DIVIDER
CPU clock
CRYSTAL OR RESONATOR
XTAL1 XTAL2 CONFIGURABLE OSCILLATOR ON-CHIP OSCILLATOR
002aaa472
Fig 1. P89LPC912 block diagram
P89LPC912_913_914_5
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Product data sheet
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
P89LPC913
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
TXD 1kB CODE FLASH internal bus UART RXD
128 BYTE DATA RAM
SPI
SPICLK MOSI MISO
P3[1:0]
PORT 3 CONFIGURABLE I/O
REAL TIME CLOCK/ SYSTEM TIMER
P2.2, P2.3, P2.5
PORT 2 CONFIGURABLE I/O
TIMER 0 TIMER 1
P1.0, P1.1, P1.5
PORT 1 CONFIGURABLE I/O
CMP1 ANALOG COMPARATORS CIN2A CIN1A CMPREF
P0.2, P0[6:4]
PORT 0 CONFIGURABLE I/O
KEYPAD INTERRUPT
WATCHDOG TIMER AND OSCILLATOR
POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
PROGRAMMABLE OSCILLATOR DIVIDER
CPU clock
CRYSTAL OR RESONATOR
XTAL1 XTAL2 CONFIGURABLE OSCILLATOR ON-CHIP OSCILLATOR
002aaa473
Fig 2. P89LPC913 block diagram
P89LPC912_913_914_5
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 -- 28 September 2007
5 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
P89LPC914
HIGH PERFORMANCE ACCELERATED 2-CLOCK 80C51 CPU
TXD 1 kB CODE FLASH internal bus UART RXD SPICLK MOSI MISO SS
128 BYTE DATA RAM
SPI
P2[5:2]
PORT 2 CONFIGURABLE I/O
REAL TIME CLOCK/ SYSTEM TIMER
P1.5, P1[2:0]
PORT 1 CONFIGURABLE I/O
TIMER 0 TIMER 1
T0
P0.2, P0[6:4]
PORT 0 CONFIGURABLE I/O
ANALOG COMPARATORS
CMP1 CIN2A CIN1A CMPREF
KEYPAD INTERRUPT POWER MONITOR (POWER-ON RESET, BROWNOUT RESET)
WATCHDOG TIMER AND OSCILLATOR
PROGRAMMABLE OSCILLATOR DIVIDER
CPU clock
ON-CHIP OSCILLATOR
002aaa474
Fig 3. P89LPC914 block diagram
P89LPC912_913_914_5
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Product data sheet
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8-bit microcontrollers with two-clock 80C51 core
6. Functional diagram
VDD VSS
KBI2
CIN2A PORT 1
T0
KBI4 KBI5 KBI6
CIN1A CMPREF CMP1
PORT 0
RST
P89LPC912
CLKOUT XTAL2 PORT 3 XTAL1 MOSI MISO PORT 2 SS SPICLK
002aaa475
Fig 4. P89LPC912 functional diagram
VDD
VSS
TXD RXD KBI2 CIN2A PORT 1 KBI4 KBI5 KBI6 CIN1A CMPREF CMP1 PORT 0 RST
P89LPC913
CLKOUT XTAL2 PORT 3 XTAL1 MOSI MISO PORT 2 SPICLK
002aaa476
Fig 5. P89LPC913 functional diagram
P89LPC912_913_914_5
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Product data sheet
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
VDD
VSS
TXD RXD KBI2 CIN2A PORT 1 KBI4 KBI5 KBI6 CIN1A CMPREF CMP1 MOSI MISO PORT 2 SS SPICLK
002aaa477
T0
PORT 0
P89LPC914
RST
Fig 6. P89LPC914 functional diagram
P89LPC912_913_914_5
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Product data sheet
Rev. 05 -- 28 September 2007
8 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
7. Pinning information
7.1 Pinning
P2.2/MOSI P2.5/SPICLK P1.5/RST VSS P0.6/CMP1/KBI6 P1.2/T0 P3.1/XTAL1
1 2 3 4 5 6 7
002aaa478
14 P2.3/MISO 13 P0.2/CIN2A/KBI2 12 P0.4/CIN1A/KBI4
P89LPC912
11 P0.5/CMPREF/KBI5 10 VDD 9 8 P2.4/SS P3.0/XTAL2/CLKOUT
Fig 7. P89LPC912 TSSOP14 pin configuration
P2.2/MOSI P2.5/SPICLK P1.5/RST VSS P0.6/CMP1/KBI6 P1.1/RXD P3.1/XTAL1
1 2 3 4 5 6 7
002aaa479
14 P2.3/MISO 13 P0.2/CIN2A/KBI2 12 P0.4/CIN1A/KBI4
P89LPC913
11 P0.5/CMPREF/KBI5 10 VDD 9 8 P1.0/TXD P3.0/XTAL2/CLKOUT
Fig 8. P89LPC913 TSSOP14 pin configuration
P2.2/MOSI P2.5/SPICLK P1.5/RST VSS P0.6/CMP1/KBI6 P1.1/RXD P1.2/T0
1 2 3 4 5 6 7
002aaa480
14 P2.3/MISO 13 P0.2/CIN2A/KBI2 12 P0.4/CIN1A/KBI4
P89LPC914
11 P0.5/CMPREF/KBI5 10 VDD 9 P1.0/TXD 8 P2.4/SS
Fig 9. P89LPC914 TSSOP14 pin configuration
P89LPC912_913_914_5
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Product data sheet
Rev. 05 -- 28 September 2007
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
7.2 Pin description
Table 4. Symbol P0.2, P0.4 to P0.6 P89LPC912 pin description Pin Type I/O Description Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below: P0.2/CIN2A/ KBI2 13 I/O I I P0.4/CIN1A/ KBI4 12 I/O I I P0.5/CMPREF/ 11 KBI5 I/O I I P0.6/CMP1/ KBI6 5 I/O O I P1.2, P1.5 P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. P0.6 -- Port 0 bit 6. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6.
I/O Port 1: Port 1 is a 2-bit I/O port with P1.2 having a user-configurable output type as (P1.2); noted below. During reset Port 1 latches are configured in the input only mode with I (P1.5) the internal pull-up disabled. The operation of the P1.2 input and outputs depends upon the port configuration selected. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. P1.2 is an open drain when used as an output. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P1.2/T0
6
I/O I/O
P1.2 -- Port 1 bit 2. (Open drain when used as an output.) T0 -- Timer/counter 0 external count input or overflow output. (Open drain when used as outputs.). P1.5 -- Port 1 bit 5. (Input only.) RST -- External Reset input during power-on or if selected via UCFG1. When functioning as a reset input a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
P1.5/RST
3
I I
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Product data sheet
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8-bit microcontrollers with two-clock 80C51 core
Table 4. Symbol
P89LPC912 pin description ...continued Pin Type I/O Description Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below:
P2.2 to P2.5
P2.2/MOSI
1
I/O I/O
P2.2 -- Port 2 bit 2. MOSI -- SPI master out slave in. When configured as master, this pin is output, when configured as slave, this pin is input. P2.3 -- Port 2 bit 3. MISO -- SPI master in slave out. When configured as master, this pin is input, when configured as slave, this pin is output. P2.4 -- Port 2 bit 4. SS -- SPI Slave select. P2.5 -- Port 2 bit 5. SPICLK -- SPI clock. When configured as master, this pin is output, when configured as slave, this pin is input. Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below:
P2.3/MISO
14
I/O I/O
P2.4/SS P2.5/SPICLK
9 2
I/O I I/O I/O
P3.0 to P3.1
I/O
P3.0/XTAL2/ CLKOUT
8
I/O O O
P3.0 -- Port 3 bit 0. XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration). CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer. P3.1 -- Port 3 bit 1. XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/system timer. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
P3.1/XTAL1
7
I/O I
VSS VDD
4 10
I I
P89LPC912_913_914_5
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Product data sheet
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Table 5. Symbol
P89LPC913 pin description Pin Type I/O Description Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:
P0.2, P0.4 to P0.6
P0.2/CIN2A/ KBI2
13
I/O I I
P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. P0.6 -- Port 0 bit 6. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. Port 1: Port 1 is a 3-bit I/O port with a user-configurable output type, except for P1.5 noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P0.4/CIN1A/ KBI4
12
I/O I I I/O I I I/O O I I/O (P1.0, P1.1); I (P1.5)
P0.5/CMPREF/ 11 KBI5
P0.6/CMP1/ KBI6
5
P1.0, P1.1, P1.5
P1.0/TXD P1.1/RXD P1.5/RST
9 6 3
I/O O I/O I I I
P1.0 -- Port 1 bit 0. TXD -- Transmitter output for the serial port. P1.1 -- Port 1 bit 1. RXD -- Receiver input for the serial port. P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
P89LPC912_913_914_5
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Product data sheet
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8-bit microcontrollers with two-clock 80C51 core
Table 5. Symbol P2.2, P2.3, P2.5
P89LPC913 pin description ...continued Pin Type I/O Description Port 2: Port 2 is a 3-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below:
P2.2/MOSI
1
I/O I/O
P2.2 -- Port 2 bit 2. MOSI -- SPI master out slave in. When configured as master, this pin is output, when configured as slave, this pin is input. P2.3 -- Port 2 bit 3. MISO -- SPI master in slave out. When configured as master, this pin is input, when configured as slave, this pin is output. P2.5 -- Port 2 bit 5. SPICLK -- SPI clock. When configured as master, this pin is output, when configured as slave, this pin is input. Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 3 also provides various special functions as described below:
P2.3/MISO
14
I/O I/O
P2.5/SPICLK
2
I/O I/O
P3.0 to P3.1
I/O
P3.0/XTAL2/ CLKOUT
8
I/O O O
P3.0 -- Port 3 bit 0. XTAL2 -- Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration). CLKOUT -- CPU clock divided by 2 when enabled via SFR bit (ENCLK - TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the Real-Time clock/system timer. P3.1 -- Port 3 bit 1. XTAL1 -- Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the Real-Time clock/system timer. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
P3.1/XTAL1
7
I/O I
VSS VDD
4 10
I I
P89LPC912_913_914_5
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Product data sheet
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8-bit microcontrollers with two-clock 80C51 core
Table 6. Symbol
P89LPC914 pin description Pin Type I/O Description Port 0: Port 0 is a 4-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. The Keypad Interrupt feature operates with Port 0 pins. All pins have Schmitt triggered inputs. Port 0 also provides various special functions as described below:
P0.2, P0.4 to P0.6
P0.2/CIN2A/ KBI2
13
I/O I I
P0.2 -- Port 0 bit 2. CIN2A -- Comparator 2 positive input A. KBI2 -- Keyboard input 2. P0.4 -- Port 0 bit 4. CIN1A -- Comparator 1 positive input A. KBI4 -- Keyboard input 4. P0.5 -- Port 0 bit 5. CMPREF -- Comparator reference (negative) input. KBI5 -- Keyboard input 5. P0.6 -- Port 0 bit 6. CMP1 -- Comparator 1 output. KBI6 -- Keyboard input 6. Port 1: Port 1 is a 4-bit I/O port with a user-configurable output type, except for three pins noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. P1.2 is an open drain when used as an output. P1.5 is input only. All pins have Schmitt triggered inputs. Port 1 also provides various special functions as described below:
P0.4/CIN1A/ KBI4
12
I/O I I I/O I I I/O O I I/O (P1.0 to P1.2); I (P1.5)
P0.5/CMPREF 11 / KBI5
P0.6/CMP1/ KBI6
5
P1.0 to P1.2, P1.5
P1.0/TXD P1.1/RXD P1.2/T0
9 6 7
I/O O I/O I I/O I/O
P1.0 -- Port 1 bit 0. TXD -- Transmitter output for the serial port. P1.1 -- Port 1 bit 1. RXD -- Receiver input for the serial port. P1.2 -- Port 1 bit 2. (Open drain when used as an output.) T0 -- Timer/counter 0 external count input or overflow output. (Open drain when used as outputs.) P1.5 -- Port 1 bit 5 (input only). RST -- External Reset input during Power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode.
P1.5/RST
3
I I
P89LPC912_913_914_5
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Product data sheet
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8-bit microcontrollers with two-clock 80C51 core
Table 6. Symbol
P89LPC914 pin description ...continued Pin Type I/O Description Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 8.12.1 "Port configurations" and Table 13 "Static characteristics" for details. All pins have Schmitt triggered inputs. Port 2 also provides various special functions as described below:
P2.2 to P2.5
P2.2/MOSI
1
I/O I/O
P2.2 -- Port 2 bit 2. MOSI -- SPI master out slave in. When configured as master, this pin is output, when configured as slave, this pin is input. P2.3 -- Port 2 bit 3. MISO -- SPI master in slave out. When configured as master, this pin is input, when configured as slave, this pin is output. P2.4 -- Port 2 bit 4. SS -- SPI Slave select. P2.5 -- Port 2 bit 5. SPICLK -- SPI clock. When configured as master, this pin is output, when configured as slave, this pin is input. Ground: 0 V reference. Power Supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes.
P2.3/MISO
14
I/O I/O
P2.4/SS P2.5/SPICLK
8 2
I/O I I/O I/O
VSS VDD
4 10
I I
P89LPC912_913_914_5
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 -- 28 September 2007
15 of 66
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
8. Functional description
Remark: Please refer to the P89LPC912/913/914 User manual for a more detailed functional description.
8.1 Special function registers
Remark: SFR accesses are restricted in the following ways:
* User must not attempt to access any SFR locations not defined. * Accesses to any defined SFR locations must be strictly for the functions for the SFRs. * SFR bits labeled `-', `0' or `1' can only be written and read as follows:
- `-' Unless otherwise specified, must be written with `0', but can return any value when read (even if it was written with `0'). It is a reserved bit and may be used in future derivatives. - `0' must be written with `0', and will return a `0' when read. - `1' must be written with `1', and will return a `1' when read.
P89LPC912_913_914_5
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 05 -- 28 September 2007
16 of 66
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Product data sheet Rev. 05 -- 28 September 2007
(c) NXP B.V. 2007. All rights reserved. P89LPC912_913_914_5
NXP Semiconductors
Table 7. P89LPC912 Special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address ACC* AUXR1 B* CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL FMCON Accumulator Auxiliary function register B register Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low Program flash address high Program flash address low Program flash control (Read) Program flash control (Write) FMDATA IEN0* IEN1* IP0* IP0H Program flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high E5H Bit address A8H Bit address E8H Bit address B8H B7H Bit address IP1* IP1H Interrupt priority 1 Interrupt priority 1 high F8H F7H AF EA EF BF FF AE EWDRT EE BE PWDRT PWDRT H FE AD EBO ED BD PBO PBOH FD AC EC BC FC AB ET1 EB ESPI BB PT1 PT1H FB PSPI PSPIH AA EA EC BA FA PC PCH A9 ET0 E9 EKBI B9 PT0 PT0H F9 PKBI PKBIH A8 E8 B8 F8 00[1] 00[1] 00x0 0000 00x0 0000 00[1] 00[1] x000 0000 x000 0000 00[1] 00x0 0000 00 0000 0000 83H 82H E7H E6H E4H BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1 OI FMCMD. 0 00 0000 0000 00 00 00 00 70 0000 0000 0000 0000 0000 0000 0000 0000 0111 0000 E0H A2H F0H ACH ADH 95H CE1 CE2 CN1 CN2 OE1 CO1 CO2 CMF1 CMF2 CLKLP F7 F6 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00[1] 00[1] 00 0000 0000 xx00 0000 xx00 0000 0000 0000 Bit address E7 E6 E5 E4 E3 E2 E1 Reset value LSB E0 00 00[1] 0000 0000 0000 00x0 Hex Binary
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
17 of 66
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Table 7. P89LPC912 Special function registers ...continued * indicates SFRs that are bit addressable. Name KBCON KBMASK KBPATN P0* Description Keypad control register Keypad interrupt mask register Keypad pattern register Port 0 SFR Bit functions and addresses addr. MSB 94H 86H 93H Bit address 80H Bit address P1*
Rev. 05 -- 28 September 2007
(c) NXP B.V. 2007. All rights reserved.
Product data sheet 18 of 66
P89LPC912_913_914_5
NXP Semiconductors
Reset value LSB PATN _SEL KBIF Hex 00[1] 00 FF Binary xxxx xx00 0000 0000 1111 1111
-
-
-
87
86 CMP1/ KB6
85 CMPREF / KB5 95 RST A5 SPICLK B5
84 CIN1A/ KB4 94 A4 SS B4
83
82 CIN2A/ KB2
81
80
[1]
97 A7 B7
96 A6 B6
93 A3 MISO B3
92 T0 A2 MOSI B2 (P0M1.2) (P0M2.2) (P1M1.2) (P1M2.2)
91 A1 B1 XTAL1
90
[1]
Port 1 Port 2 Port 3 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Port 3 output mode 1 Port 3 output mode 2 Power control register Power control register A Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register high
90H Bit address A0H Bit address B0H 84H 85H 91H 92H A4H A5H B1H B2H 87H B5H Bit address D0H F6H DFH D1H D2H RTCPD D7 CY RTCF D6 AC RTCS1
A0
[1]
P2* P3* P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 PCON PCONA PSW* PT0AD RSTSRC RTCCON RTCH
B0 XTAL2
[1]
(P0M1.6) (P0M1.5) (P0M1.4) (P0M2.6) (P0M2.5) (P0M2.4)
FF 00 D3[1] 00[1] FF 00 (P3M1.1) (P3M1.0) 03[1] 00 00[1] 00 00
[2]
1111 1111
8-bit microcontrollers with two-clock 80C51 core
0000 0000 11x1 xx11 00x0 xx00 1111 1111 0000 0000 xxxx xx11 xxxx xx00 0000 0000 0000 0000 0000 0000 xx00 000x 011x xx00 0000 0000
P89LPC912/913/914
(P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2)
(P3M2.1) (P3M2.0) 00[1] BOPD VCPD D5 F0 BOF RTCS0 BOI D4 RS1 POF GF1 D3 RS0 GF0 SPPD D2 OV PT0AD.2 R_WD PMOD1 D1 F1 R_SF ERTC PMOD0 D0 P R_EX RTCEN
PT0AD.5 PT0AD.4
60[1][5] 00[5]
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Table 7. P89LPC912 Special function registers ...continued * indicates SFRs that are bit addressable. Name RTCL SP SPCTL SPSTAT SPDAT TAMOD TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON WDL WFEED1 WFEED2
[1] [2] [3] [4] [5]
(c) NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 -- 28 September 2007 19 of 66
P89LPC912_913_914_5
NXP Semiconductors
Description Real-time clock register low Stack pointer SPI control register SPI status register SPI data register Timer 0 and 1 auxiliary mode Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register Watchdog load Watchdog feed 1 Watchdog feed 2
SFR Bit functions and addresses addr. MSB D3H 81H E2H E1H E3H 8FH 88H 8CH 8DH 8AH 8BH 89H 96H A7H C1H C2H C3H PRE2 ENCLK PRE1 T1M1 TRIM.5 PRE0 T1M0 TRIM.4 T0GATE TRIM.3 T0C/T TRIM.2 WDRUN T0M1 TRIM.1 WDTOF 8F TF1 8E TR1 8D TF0 8C TR0 8B 8A 89 SSIG SPIF SPEN WCOL DORD MSTR CPOL CPHA SPR1 -
Reset value LSB Hex 00[5] 07 SPR0 T0M2 88 00 00 00 00 00 T0M0 TRIM.0 WDCLK 00
[4] [5] [3] [5]
Binary 0000 0000 0000 0111 0000 0100 00xx xxxx 0000 0000 xxx0 xxx0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
04 00 00 00
Bit address
8-bit microcontrollers with two-clock 80C51 core
FF
1111 1111
P89LPC912/913/914
All ports are in input only (high impedance) state after power-up. The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
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Product data sheet Rev. 05 -- 28 September 2007
(c) NXP B.V. 2007. All rights reserved. P89LPC912_913_914_5
NXP Semiconductors
Table 8. P89LPC913 Special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address ACC* AUXR1 B* BRGR0[2] BRGR1[2] BRGCON CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL FMCON Accumulator Auxiliary function register B register Baud rate generator rate low Baud rate generator rate high Baud rate generator control Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low Program flash address high Program flash address low Program flash control (Read) Program flash control (Write) FMDATA IEN0* IEN1* IP0* IP0H Program flash data Interrupt enable 0 Interrupt enable 1 Interrupt priority 0 Interrupt priority 0 high E5H Bit address A8H Bit address E8H Bit address B8H B7H AF EA EF BF AE EWDRT EE EST BE PWDRT PWDRT H AD EBO ED BD PBO PBOH AC ES/ESR EC BC PS/PSR PSH/ PSRH AB ET1 EB ESPI BB PT1 PT1H AA EA EC BA A9 ET0 E9 EKBI B9 PT0 PT0H A8 E8 B8 00[1] 00[1] x000 0000 x000 0000 00[1] 00x0 0000 00 0000 0000 83H 82H E7H E6H E4H BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1 OI FMCMD. 0 00 0000 0000 00 00 00 00 70 0000 0000 0000 0000 0000 0000 0000 0000 0111 0000 E0H A2H F0H BEH BFH BDH ACH ADH 95H CE1 CE2 CN1 CN2 OE1 SBRGS CO1 BRGEN CMF1 CMF2 CLKLP F7 EBRR F6 F5 F4 SRST F3 0 F2 F1 DPS F0 00 00 00 00[6] 00[1] 00[1] 00 0000 0000 0000 0000 0000 0000 xxxx xx00 xx00 0000 xx00 0000 0000 0000 Bit address E7 E6 E5 E4 E3 E2 E1 Reset value LSB E0 00 00[1] 0000 0000 0000 00x0 Hex Binary
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
20 of 66
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Table 8. P89LPC913 Special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address IP1* IP1H KBCON KBMASK KBPATN P0*
Rev. 05 -- 28 September 2007
(c) NXP B.V. 2007. All rights reserved.
Product data sheet 21 of 66
P89LPC912_913_914_5
NXP Semiconductors
Reset value LSB FC FB PSPI PSPIH FA PC PCH F9 PKBI PKBIH PATN _SEL F8 KBIF 00[1] 00[1] 00[1] 00 FF 00x0 0000 00x0 0000 xxxx xx00 0000 0000 1111 1111 Hex Binary
FF -
FE PST PSTH -
FD -
Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register Port 0
F8H F7H 94H 86H 93H Bit address 80H Bit address
87
86 CMP1/ KB6
85 CMPREF / KB5 95 RST A5 SPICLK B5
84 CIN1A/ KB4 94 A4 B4
83
82 CIN2A/ KB2
81
80
[1]
97 A7 B7
96 A6 B6
93 A3 MISO B3
92 A2 MOSI B2 (P0M1.2) (P0M2.2)
91 RXD A1 B1 XTAL1
90 TXD A0
[1] [1]
P1* P2* P3* P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 P3M1 P3M2 PCON PCONA
Port 1 Port 2 Port 3 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Port 3 output mode 1 Port 3 output mode 2 Power control register Power control register A
90H Bit address A0H Bit address B0H 84H 85H 91H 92H A4H A5H B1H B2H 87H B5H SMOD1 RTCPD SMOD0 -
8-bit microcontrollers with two-clock 80C51 core
B0 XTAL2
[1]
(P0M1.6) (P0M1.5) (P0M1.4) (P0M2.6) (P0M2.5) (P0M2.4)
FF 00 (P1M1.1) (P1M1.0) (P1M2.1) (P1M2.0) D3[1] 00[1] FF 00 (P3M1.1) (P3M1.0) (P3M2.1) (P3M2.0) 03[1] 00[1] 00 00[1]
1111 1111 0000 0000 11x1 xx11 00x0 xx00 1111 1111 0000 0000 xxxx xx11 xxxx xx00 0000 0000 0000 0000
P89LPC912/913/914
(P2M1.5) (P2M2.5)
(P2M1.3) (P2M1.2) (P2M2.3) (P2M2.2)
BOPD VCPD
BOI -
GF1 -
GF0 SPPD
PMOD1 SPD
PMOD0 -
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Table 8. P89LPC913 Special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF
Rev. 05 -- 28 September 2007
(c) NXP B.V. 2007. All rights reserved.
Product data sheet 22 of 66
P89LPC912_913_914_5
NXP Semiconductors
Reset value LSB D4 RS1 POF D3 RS0 R_BK D2 OV PT0AD.2 R_WD D1 F1 R_SF ERTC D0 P R_EX RTCEN 00 00
[3]
Hex
Binary 0000 0000 xx00 000x 011x xx00 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx
D7 CY RTCF
D6 AC RTCS1
D5 F0 BOF RTCS0
Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register low Serial port address register Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer SPI control register SPI status register SPI data register Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register
D0H F6H DFH D1H D2H D3H A9H B9H 99H Bit address
PT0AD.5 PT0AD.4
60[1][6] 00[6] 00[6] 00 00 xx
9F SM0/FE DBMOD
9E SM1 INTLO
9D SM2 CIDIS
9C REN DBISEL
9B TB8 FE
9A RB8 BR
99 TI OE
98 RI STINT 00 00 07 0000 0000 0000 0000
SCON SSTAT SP SPCTL SPSTAT SPDAT TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON
98H BAH 81H E2H E1H E3H Bit address 88H 8CH 8DH 8AH 8BH 89H 96H A7H
8-bit microcontrollers with two-clock 80C51 core
0000 0111 0000 0100 00xx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
SSIG SPIF 8F TF1
SPEN WCOL 8E TR1
DORD 8D TF0
MSTR 8C TR0
CPOL 8B -
CPHA 8A -
SPR1 89 -
SPR0 88 -
04 00 00 00 00 00 00 00
P89LPC912/913/914
PRE2
ENCLK PRE1
T1M1 TRIM.5 PRE0
T1M0 TRIM.4 -
T0GATE TRIM.3 -
T0C/T TRIM.2 WDRUN
T0M1 TRIM.1 WDTOF
T0M0 TRIM.0 WDCLK
00
[5] [6] [4] [6]
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Table 8. P89LPC913 Special function registers ...continued * indicates SFRs that are bit addressable. Name WDL WFEED1 WFEED2
[1] [2] [3] [4] [5] Rev. 05 -- 28 September 2007
(c) NXP B.V. 2007. All rights reserved.
Product data sheet 23 of 66
P89LPC912_913_914_5
NXP Semiconductors
Description Watchdog load Watchdog feed 1 Watchdog feed 2
SFR Bit functions and addresses addr. MSB C1H C2H C3H
Reset value LSB Hex FF Binary 1111 1111
All ports are in input only (high impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any of them is written if BRGEN = 1, result is unpredictable. The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
[6]
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
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Product data sheet Rev. 05 -- 28 September 2007
(c) NXP B.V. 2007. All rights reserved. P89LPC912_913_914_5
NXP Semiconductors
Table 9. P89LPC914 Special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address ACC* AUXR1 B* BRGR0[2] BRGR1[2] BRGCON CMP1 CMP2 DIVM DPTR DPH DPL FMADRH FMADRL FMCON Accumulator Auxiliary function register B register Baud rate generator rate low Baud rate generator rate high Baud rate generator control Comparator 1 control register Comparator 2 control register CPU clock divide-by-M control Data pointer (2 bytes) Data pointer high Data pointer low Program flash address high Program flash address low Program flash control (Read) Program flash control (Write) FMDATA IEN0* IEN1* Program flash data Interrupt enable 0 Interrupt enable 1 E5H Bit address A8H Bit address E8H AF EA EF AE EWDRT EE EST AD EBO ED AC ES/ESR EC AB ET1 EB ESPI AA EA EC A9 ET0 E9 EKBI A8 E8 00[1] 00x0 0000 00 0000 0000 83H 82H E7H E6H E4H BUSY FMCMD. 7 FMCMD. 6 FMCMD. 5 FMCMD. 4 HVA FMCMD. 3 HVE FMCMD. 2 SV FMCMD. 1 OI FMCMD. 0 00 0000 0000 00 00 00 00 70 0000 0000 0000 0000 0000 0000 0000 0000 0111 0000 E0H A2H F0H BEH BFH BDH ACH ADH 95H CE1 CE2 CN1 CN2 OE1 SBRGS CO1 CO2 BRGEN CMF1 CMF2 F7 EBRR F6 F5 ENT0 F4 SRST F3 0 F2 F1 DPS F0 00 00 00 00[6] 00[1] 00[1] 00 0000 0000 0000 0000 0000 0000 xxxx xx00 xx00 0000 xx00 0000 0000 0000 Bit address E7 E6 E5 E4 E3 E2 E1 Reset value LSB E0 00 00[1] 0000 0000 0000 00x0 Hex Binary
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
24 of 66
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Table 9. P89LPC914 Special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address IP0* IP0H Interrupt priority 0 Interrupt priority 0 high B8H B7H Bit address IP1* IP1H KBCON KBMASK
Rev. 05 -- 28 September 2007
(c) NXP B.V. 2007. All rights reserved.
Product data sheet 25 of 66
P89LPC912_913_914_5
NXP Semiconductors
Reset value LSB BC PS/PSR PSH/ PSRH FC BB PT1 PT1H FB PSPI PSPIH BA FA PC PCH B9 PT0 PT0H F9 PKBI PKBIH PATN_S EL B8 F8 KBIF 00[1] 00[1] 00[1] 00 FF 00x0 0000 00x0 0000 xxxx xx00 0000 0000 1111 1111 00[1] 00[1] x000 0000 x000 0000 Hex Binary
BF FF -
BE PWDRT PWDRT H FE PST PSTH -
BD PBO PBOH FD -
Interrupt priority 1 Interrupt priority 1 high Keypad control register Keypad interrupt mask register Keypad pattern register Port 0
F8H F7H 94H 86H 93H Bit address
KBPATN P0*
87
86 CMP1/ KB6
85 CMPREF / KB5 95 RST A5 SPICLK
84 CIN1A/ KB4 94 A4 SS
83
82 CIN2A/ KB2
81
80
[1]
80H Bit address 97 A7
96 A6
93 A3 MISO
92 T0 A2 MOSI (P0M1.2) (P0M2.2)
91 RXD A1
90 TXD A0
[1] [1]
8-bit microcontrollers with two-clock 80C51 core
P1* P2* P0M1 P0M2 P1M1 P1M2 P2M1 P2M2 PCON PCONA
Port 1 Port 2 Port 0 output mode 1 Port 0 output mode 2 Port 1 output mode 1 Port 1 output mode 2 Port 2 output mode 1 Port 2 output mode 2 Power control register Power control register A
90H Bit address A0H 84H 85H 91H 92H A4H A5H 87H B5H SMOD1 RTCPD SMOD0 -
P89LPC912/913/914
(P0M1.6) (P0M1.5) (P0M1.4) (P0M2.6) (P0M2.5) (P0M2.4)
FF 00
1111 1111 0000 0000 11x1 xx11 00x0 xx00 1111 1111 0000 0000 0000 0000 0000 0000
(P1M1.2) (P1M1.1) (P1M1.0) D3[1] (P1M2.2) (P1M2.1) (P1M2.0) 00[1] (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) BOPD VCPD BOI GF1 GF0 SPPD PMOD1 SPD PMOD0 FF 00 00 00[1]
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Table 9. P89LPC914 Special function registers ...continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address PSW* PT0AD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF
Rev. 05 -- 28 September 2007
(c) NXP B.V. 2007. All rights reserved.
Product data sheet 26 of 66
P89LPC912_913_914_5
NXP Semiconductors
Reset value LSB D4 RS1 POF D3 RS0 R_BK D2 OV PT0AD.2 R_WD D1 F1 R_SF ERTC D0 P R_EX RTCEN 00 00
[3]
Hex
Binary 0000 0000 xx00 000x 011x xx00 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx
D7 CY RTCF
D6 AC RTCS1
D5 F0 BOF RTCS0
Program status word Port 0 digital input disable Reset source register Real-time clock control Real-time clock register high Real-time clock register low Serial port address register Serial port address enable Serial port data buffer register Serial port control Serial port extended status register Stack pointer SPI control register SPI status register SPI data register Timer 0 and 1 auxiliary mode Timer 0 and 1 control Timer 0 high Timer 1 high Timer 0 low Timer 1 low Timer 0 and 1 mode Internal oscillator trim register Watchdog control register
D0H F6H DFH D1H D2H D3H A9H B9H 99H Bit address
PT0AD.5 PT0AD.4
60[1][6] 00[6] 00[6] 00 00 xx
9F SM0/FE DBMOD
9E SM1 INTLO
9D SM2 CIDIS
9C REN DBISEL
9B TB8 FE
9A RB8 BR
99 TI OE
98 RI STINT 00 00 07 0000 0000 0000 0000
SCON SSTAT SP SPCTL SPSTAT SPDAT TAMOD TCON* TH0 TH1 TL0 TL1 TMOD TRIM WDCON
98H BAH 81H E2H E1H E3H 8FH 88H 8CH 8DH 8AH 8BH 89H 96H A7H
8-bit microcontrollers with two-clock 80C51 core
0000 0111 0000 0100 00xx xxxx 0000 0000 xxx0 xxx0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
SSIG SPIF 8F TF1
SPEN WCOL 8E TR1
DORD 8D TF0
MSTR 8C TR0
CPOL 8B -
CPHA 8A -
SPR1 89 -
SPR0 T0M2 88 -
04 00 00 00 00 00 00 00 00
P89LPC912/913/914
Bit address
PRE2
PRE1
T1M1 TRIM.5 PRE0
T1M0 TRIM.4 -
T0GATE TRIM.3 -
T0C/T TRIM.2 WDRUN
T0M1 TRIM.1 WDTOF
T0M0 TRIM.0 WDCLK
00
[5] [6] [4] [6]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 9. P89LPC914 Special function registers ...continued * indicates SFRs that are bit addressable. Name WDL WFEED1 WFEED2
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Description Watchdog load Watchdog feed 1 Watchdog feed 2
SFR Bit functions and addresses addr. MSB C1H C2H C3H
Reset value LSB Hex FF Binary 1111 1111
All ports are in input only (high impedance) state after power-up. BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any of them is written if BRGEN = 1, result is unpredictable. The RSTSRC register reflects the cause of the P89LPC912 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is xx11 0000. After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset. Other resets will not affect WDTOF. On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register. The only reset source that affects these SFRs is power-on reset.
[6]
8-bit microcontrollers with two-clock 80C51 core
P89LPC912/913/914
NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
8.2 Enhanced CPU
The P89LPC912/913/914 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
8.3 Clocks
8.3.1 Clock definitions
The P89LPC912/913/914 device has several internal clocks as defined below: OSCCLK -- Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 10, 11, and 12) and can also be optionally divided to a slower frequency (see Section 8.8 "CCLK modification: DIVM register"). Note: fosc is defined as the OSCCLK frequency. CCLK -- CPU clock; output of the clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles). RCCLK -- The internal 7.373 MHz RC oscillator output. PCLK -- Clock for the various peripheral devices and is CCLK/2
8.3.2 CPU clock (OSCCLK)
The P89LPC912/913/914 provide user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator and an on-chip RC oscillator. In addition, both the P89LPC912 and P89LPC913 provide an oscillator using an external crystal or an external clock source. The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.
8.3.3 Low-speed oscillator option (P89LPC912, P89LPC913)
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration.
8.3.4 Medium-speed oscillator option (P89LPC912, P89LPC913)
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.
8.3.5 High-speed oscillator option (P89LPC912, P89LPC913)
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
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8-bit microcontrollers with two-clock 80C51 core
8.3.6 Clock output (P89LPC912, P89LPC913)
The P89LPC912 supports a user selectable clock output function on the XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if another clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-Time clock is not using the crystal oscillator as its clock source. This allows external devices to synchronize to the P89LPC912. This output is enabled by the ENCLK bit in the TRIM register. The frequency of this clock output is 12 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power.
8.4 On-chip RC oscillator option
The P89LPC912/913/914 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz, 1 % at room temperature. End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies.
8.5 Watchdog oscillator option
The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator can be used to save power when a high clock frequency is not needed.
8.6 External clock input option (P89LPC912, P89LPC913)
In this configuration, the processor clock is derived from an external source driving the XTAL1/P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2/P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed, VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
XTAL1 XTAL2
HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY
RTC
oscclk rcclk RC OSCILLATOR (7.3728 MHz 1 %) WATCHDOG OSCILLATOR (400 kHz + 30 % - 20 %) pclk DIVM
cclk CPU /2 pclk WDT
SPI
TIMER 0/ TIMER 1
002aaa481
Fig 10. Block diagram of oscillator control (P89LPC912)
XTAL1 XTAL2
HIGH FREQUENCY MEDIUM FREQUENCY LOW FREQUENCY
RTC
oscclk rcclk RC OSCILLATOR (7.3728 MHz 1 %) WATCHDOG OSCILLATOR (400 kHz + 30 % - 20 %) pclk DIVM
cclk CPU /2 pclk WDT
SPI
TIMER 0/ TIMER 1
BAUDRATE GENERATOR
UART
002aaa482
Fig 11. Block diagram of oscillator control (P89LPC913)
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8-bit microcontrollers with two-clock 80C51 core
RTC
rcclk oscclk DIVM RC OSCILLATOR (7.3728 MHz 1 %) WATCHDOG OSCILLATOR (400 kHz + 30 % - 20 %) pclk pclk WDT /2 cclk CPU
SPI
TIMER 0/ TIMER 1
BAUDRATE GENERATOR
UART
002aaa483
Fig 12. Block diagram of oscillator control (P89LPC914)
8.7 CCLK wake-up delay
The P89LPC912/913/914 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (P89LPC912, P89LPC913) the delay is 992 OSCCLK cycles plus 60 s to 100 s. If the clock source is either the internal RC oscillator, watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 s to 100 s.
8.8 CCLK modification: DIVM register
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events that would not exit Idle mode by executing its normal program at a lower rate. This can also allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.
8.9 Low power select
The P89LPC912 and P89LPC913 are designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
8.10 Memory organization
The various P89LPC912/913/914 memory spaces are as follows:
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8-bit microcontrollers with two-clock 80C51 core
* DATA
128 B of internal data memory space (00H:7FH) accessed via direct or indirect addressing, using instructions other than MOVX and MOVC. All or part of the Stack may be in this area.
* SFR
Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.
* CODE
64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC912/913/914 has 1 kB of on-chip Code memory.
8.11 Interrupts
The P89LPC912/913/914 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC912 supports 7 interrupt sources: timers 0 and 1, brownout detect, Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI. The P89LPC913 and P89LPC914 devices support 10 interrupt sources: timers 0 and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect, Watchdog/Real-Time clock, keyboard, comparators 1 and 2, and SPI. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global disable bit, EA, which disables all interrupts. Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the start of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used to resolve pending requests of the same priority level.
8.11.1 External interrupt inputs
The P89LPC912/913/914 has a Keypad Interrupt function. This can be used as an external interrupt input. If enabled when the P89LPC912/913/914 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 8.14 "Power reduction modes" for details.
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BOF EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7)
wake-up (if in power-down)
TF0 ET0 TF1 ET1 SPIF ESPI
interrupt to CPU
002aaa484
Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC912)
BOF EBO RTCF ERTC (RTCCON.1) WDOVF KBIF EKBI EWDRT CMF2 CMF1 EC EA (IE0.7) TF0 ET0 TF1 ET1 TI and RI/RI ES/ESR TI EST SPIF ESPI
002aaa485
wake-up (if in power-down)
interrupt to CPU
Fig 14. Interrupt sources, interrupt enables, and power-down wake-up sources (P89LPC913, P89LPC914)
8.12 I/O ports
The P89LPC912 and P89LPC913 devices have 4 I/O ports: Port 0, Port 1, Port 2 and Port 3. The exact number of I/O pins available depends on the clock and reset options chosen, as shown in Table 10.
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8-bit microcontrollers with two-clock 80C51 core
Number of I/O pins available (P89LPC912, P89LPC913) Reset option Number of I/O pins (14-pin package) 11 10 9
Table 10.
Clock source
On-chip oscillator or watchdog oscillator External clock input Low/medium/high-speed oscillator (external crystal or resonator)
[1] Required for operation above 12 MHz.
No external reset (except during power-up) 12 External RST pin supported External RST pin supported External RST pin supported[1] No external reset (except during power-up) 11 No external reset (except during power-up) 10
The P89LPC914 has three I/O ports: Port 0, Port 1, and Port 2. The exact number of I/O pins available depends upon the reset option chosen, as shown in Table 11.
Table 11. Number of I/O pins available (P89LPC914) Number of I/O pins (14-pin package) 12 11 supported[1]
Reset option No external reset (except during power-up) External RST pin
[1]
Required for operation above 12 MHz.
8.12.1 Port configurations
Except as listed below, every I/O pin on the P89LPC912/913/914 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port select the output type for each port pin. P1.5/RST can only be an input and cannot be configured. P1.2/T0 may only be configured to be either input-only or open drain (P89LPC912, P89LPC914).
8.12.2 Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the pin is driven LOW, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open-drain output except that there are three pull-up transistors in the quasi-bidirectional output that serve different purposes. The P89LPC912/913/914 is a 3 V device, but the pins are 5 V-tolerant. In quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current flowing from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in quasi-bidirectional mode is discouraged. A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit.
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8.12.3 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. An open-drain port pin has a Schmitt triggered input that also has a glitch suppression circuit.
8.12.4 Input-only configuration
The input-only port configuration has no output drivers. It is a Schmitt triggered input that also has a glitch suppression circuit.
8.12.5 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. A push-pull port pin has a Schmitt triggered input that also has a glitch suppression circuit.
8.12.6 Port 0 analog functions
The P89LPC912/913/914 incorporates two Analog Comparators. In order to give the best analog function performance and to minimize power consumption, pins that are being used for analog functions must have the digital outputs and digital inputs disabled. Digital outputs are disabled by putting the port output into the Input-only (high-impedance) mode as described in Section 8.12.4 "Input-only configuration". Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any reset, the PT0AD bits default to logic 0s to enable digital functions.
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8.12.7 Additional port features
After power-up, all pins are in Input-Only mode. After power-up all I/O pins except P1.5, may be configured by software.
* Pin P1.5 is input only. * P1.2/T0 is configurable for either input-only or open-drain (P89LPC912, P89LPC914).
Every output on the P89LPC912/913/914 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to Table 13 "Static characteristics" for detailed specifications. All port pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
8.13 Power monitoring functions
The P89LPC912/913/914 incorporates power monitoring functions designed to prevent incorrect operation during initial power-up and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on detect and brownout detect.
8.13.1 Brownout detection
The brownout detect function determines if the power supply voltage drops below a certain level. The default operation is for a brownout detection to cause a processor reset, however, it may alternatively be configured to generate an interrupt. Brownout detection may be enabled or disabled in software. If brownout detection is enabled, the brownout condition occurs when VDD falls below the brownout trip voltage, Vbo (see Table 13 "Static characteristics"), and is negated when VDD rises above Vbo. If the P89LPC912/913/914 device is to operate with a power supply that can be below 2.7 V, BOE should be left in the unprogrammed state so that the device can operate at 2.4 V, otherwise continuous brownout reset may prevent the device from operating. For correct activation of Brownout detect, the VDD rise and fall times must be observed. Please see Table 13 "Static characteristics" for specifications.
8.13.2 Power-on detection
The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software.
8.14 Power reduction modes
The P89LPC912/913/914 supports three different power reduction modes. These modes are Idle mode, Power-down mode, and Total Power-down mode.
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8-bit microcontrollers with two-clock 80C51 core
8.14.1 Idle mode
Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.
8.14.2 Power-down mode
The Power-down mode stops the oscillator in order to minimize power consumption. The P89LPC912/913/914 exits Power-down mode via any reset, or certain interrupts. In Power-down mode, the power supply voltage may be reduced to the RAM data retention voltage VDDR. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after VDD has been lowered to VDDR, therefore it is highly recommended to wake up the processor via reset in this case. VDD must be raised to within the operating range before the Power-down mode is exited. Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include: Brownout detect, watchdog timer, comparators (note that comparators can be powered-down separately), and RTC/System Timer. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled.
8.14.3 Total Power-down mode
This is the same as Power-down mode except that the brownout detection circuitry and the voltage comparators are also disabled to conserve additional power. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during power-down, there will be high power consumption. Please use an external low frequency clock to achieve low power with the RTC running during power-down.
8.15 Reset
The P1.5/RST pin can function as either an active-LOW reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to logic 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. Remark: During a power-up sequence, the RPE selection is overridden and this pin will always function as a reset input. An external circuit connected to this pin should not hold this pin LOW during a power-on sequence as this will keep the device in reset. After power-up this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit.
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Reset can be triggered from the following sources:
* External reset pin (during power-up or if user configured via UCFG1. This option must
be used for an oscillator frequency above 12 MHz.)
* * * * *
Power-on detect Brownout detect Watchdog timer Software reset UART break character detect reset (P89LPC913, P89LPC914).
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
* During a power-on reset, both POF and BOF are set but the other flag bits are
cleared.
* For any other reset, previously set flag bits that have not been cleared will remain set. 8.16 Timers/counters 0 and 1
The P89LPC912/913/914 devices have two general purpose counter/timers which are upward compatible with the standard 80C51 Timer 0 and Timer 1. An option to automatically toggle the T0 pin upon timer overflow has been added (P89LPC912, P89LPC914). In the `Timer' function, the register is incremented every machine cycle. In the `Counter' function, the register of Timer 0 is incremented in response to a 1-to-0 transition at its external input pin, T0. This external input is sampled once very machine cycle. Timer 0 has four operating modes (modes 0, 1, 2, and 3) on the P89LPC913). Timer 0 has five operating modes (modes 0, 1, 2, 3, and 6 on the P89LPC912 and P89LPC914. Timer 1 has four operating modes (modes 0, 1, 2, and 3) on all devices. Modes 0, 1, and 2 are the same for both Timers/Counters. Mode 3 is different.
8.16.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
8.16.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
8.16.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1.
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8.16.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit counters and is provided for applications that require an extra 8-bit timer. When Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
8.16.5 Mode 6 (P89LPC912, P89LPC914)
In this mode, the corresponding timer can be changed to a PWM with a full period of 256 timer clocks.
8.16.6 Timer overflow toggle output (P89LPC912, P89LPC914)
Timers 0 can be configured to automatically toggle the T0 output whenever a timer overflow occurs. The same device pins that are used for the T0 count input is also used for the timer toggle outputs. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on.
8.17 RTC/system timer
The P89LPC912/913/914 devices have a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered-down. The RTC can be a wake-up or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF flag will be set. On the P89LPC914 the clock source for this counter is the CPU clock (CCLK). On the P89LPC912 and P89LPC913 devices, the clock source for this counter can either be the CPU clock (CCLK) or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as its clock source. Only power-on reset will reset the RTC and its associated SFRs to the default state.
8.18 UART (P89LPC913, P89LPC914)
The P89LPC913 and P89LPC914 devices have an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC913 does include an independent Baud Rate Generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, automatic address recognition, selectable double buffering and several interrupt options. The UART can be operated in four modes: shift register, 8-bit UART, 9-bit UART, and CCLK/32 or CCLK/16.
8.18.1 Mode 0
Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at 116 of the CPU clock frequency.
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8-bit microcontrollers with two-clock 80C51 core
8.18.2 Mode 1
10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in Section 8.18.5 "Baud rate generator and selection").
8.18.3 Mode 2
11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop bit is not saved. The baud rate is programmable to either 116 or 132 of the CCLK frequency, as determined by the SMOD1 bit in PCON.
8.18.4 Mode 3
11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in section Section 8.18.5 "Baud rate generator and selection").
8.18.5 Baud rate generator and selection
The P89LPC913 and P89LPC914 devices have an independent Baud Rate Generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other timing functions. The UART can use either Timer 1 or the baud rate generator output (see Figure 15). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The independent Baud Rate Generator uses CCLK.
timer 1 overflow (PCLK-based) /2
SMOD1 = 1
SBRGS = 0 baud rate modes 1 and 3
SMOD1 = 0 baud rate generator (CCLK-based)
SBRGS = 1
002aaa419
Fig 15. Baud rate sources for UART (Modes 1, 3)
8.18.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is logic 1, framing errors can be made available in SCON.7, respectively. If SMOD0 is logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are set up when SMOD0 is logic 0.
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8.18.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when 11 consecutive bits are sensed LOW. The break detect can be used to reset the device.
8.18.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to SnBUF while the previous data is being shifted out. Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).
8.18.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TX interrupt is generated when the double buffer is ready to receive new data.
8.18.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until the bit is shifted out, as indicated by the TX interrupt. If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data.
8.19 Serial Peripheral Interface (SPI)
P89LPC912/913/914 provides another high-speed serial communication interface--the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 4.5 Mbit/s can be supported in Master mode or 3 Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection.
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CPU clock 8 BIT SHIFT REGISTER DIVIDER BY 4, 16, 64, 128 READ DATA BUFFER
S M M S PIN CONTROL LOGIC
MISO P2.3
MOSI P2.2 SPICLK P2.5 SS P2.4
clock SELECT SPR1 SPR0 MSTR SPI CONTROL SPEN DORD MSTR CPHA CPOL SPEN SPR1 SPR0 SSIG MSTR SPEN SPI clock master CLOCK LOGIC S M
SPIF
WCOL
SPI CONTROL REGISTER SPI STATUS REGISTER
SPI interrupt request
internal data bus
002aaa497
Fig 16. SPI block diagram (P89LPC912, P89LPC914)
CPU clock 8 BIT SHIFT REGISTER DIVIDER BY 4, 16, 64, 128 READ DATA BUFFER
S M M S PIN CONTROL LOGIC
MISO P2.3
MOSI P2.2
clock SELECT SPR1 SPR0 MSTR SPI CONTROL SPEN DORD MSTR CPHA CPOL SPEN SPR1 SPR0 SSIG MSTR SPEN SPI clock master CLOCK LOGIC S M
SPICLK P2.5
SPIF
WCOL
SPI CONTROL REGISTER SPI STATUS REGISTER
SPI interrupt request
internal data bus
002aaa498
Fig 17. SPI block diagram (P89LPC913)
The SPI interface has four pins: SPICLK, MOSI, MISO, and SS:
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* SPICLK, MOSI and MISO are typically tied together between two or more SPI
devices. Data flows from master to slave on MOSI (Master Out Slave In) pin and flows from slave to master on MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.
* SS is the optional slave select pin. In a typical configuration, an SPI master asserts
one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. Typical connections are shown in Figure 18, 19, and 20.
* The P89LPC913 does not have the slave select pin, SS. The SPI interface is set to
Master mode and an I/O pin may be used to implement the SS function. Typical connections are shown in Figure 18 and Figure 19.
8.19.1 Typical SPI configurations
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR PORT
SPICLK SS
002aaa901
Fig 18. SPI single master single slave configuration
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master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR port
SPICLK SS
slave MISO MOSI 8-BIT SHIFT REGISTER
SPICLK port SS
002aaa903
Fig 19. SPI single master multiple slaves configuration
master MISO 8-BIT SHIFT REGISTER MOSI MISO MOSI
slave
8-BIT SHIFT REGISTER
SPICLK SPI CLOCK GENERATOR SS
SPICLK SS SPI CLOCK GENERATOR
002aaa902
Fig 20. SPI dual device configuration, where either can be a master or a slave
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8.20 Analog comparators
Two analog comparators are provided on the P89LPC912/913/914. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes. Comparator 1 may be output to a port pin. The overall connections to both comparators are shown in Figure 21. The comparators function to VDD = 2.4 V. When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.
comparator 1 (P0.4) CIN1A (P0.5) CMPREF Vref(bg) CN1 CO1
OE1
CMP1 (P0.6) change detect CMF1
interrupt change detect CMF2 comparator 2 (P0.2) CIN2A EC
CN2
002aaa496
Fig 21. Comparator input and output connections
8.21 Internal reference voltage
An internal reference voltage generator may supply a default reference when a single comparator input pin is used. The value of the internal reference voltage, referred to as Vref(bg), is 1.23 V 3 %.
8.22 Comparator interrupt
Each comparator has an interrupt flag contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. If both comparators enable interrupts, after entering the interrupt service routine, the user needs to read the flags to determine which comparator caused the interrupt. Possible comparator configurations are shown in Figure 22.
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CIN1A CMPREF
CO1
002aaa490
CIN1A CMPREF
CO1
CMP1
002aaa491
a. CN1, OE1 = 0 0
CIN1A VREF (1.23 V)
b. CN1, OE1 = 0 1
CIN1A VREF (1.23 V) CO1
CO1
002aaa492
CMP1
002aaa493
c. CN1, OE1 = 1 0
CIN2A CMPREF
d. CN1, OE1 = 1 1
CIN2A VREF (1.23 V)
CO2
002aaa494
CO2
002aaa495
e. CN2 = 0 Fig 22. Comparator configurations
f. CN2 = 1
8.23 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode. If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place. Comparators consume power in Power-down and Idle modes, as well as in the normal operating mode. This fact should be taken into account when system power consumption is an issue. To minimize power consumption, the user can disable the comparators via PCONA.5, or put the device in Total Power-down mode.
8.24 Keypad interrupt
The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks. The Keypad Interrupt Mask Register (KBMASK) is used to define which input pins connected to Port 0 can trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt Control Register (KBCON) is set when the condition is matched while the Keypad Interrupt function is active. An interrupt will be generated if enabled. The PATN_SEL bit in the Keypad Interrupt Control Register (KBCON) is used to define equal or not-equal for the comparison.
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In order to use the Keypad Interrupt as an original KBI function like in 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 1 (not equal), then any key connected to Port 0 which is enabled by the KBMASK register will cause the hardware to set KBIF and generate an interrupt if it has been enabled. The interrupt may be used to wake up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery-powered systems that need to carefully manage power consumption yet also need to be convenient to use. In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs.
8.25 Watchdog timer
The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler. The clock source for the prescaler is either the PCLK or the nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a power-on reset. When the watchdog feature is disabled, it can be used as an interval timer and may generate an interrupt. Figure 23 shows the watchdog timer in Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered-down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few s to a few seconds. Please refer to the P89LPC912/913/914 User manual for more details.
WDL (C1H)
MOV WFEED1, #0A5H MOV WFEED2, #05AH watchdog oscillator PCLK
/32
PRESCALER
8-BIT DOWN COUNTER
reset(1)
SHADOW REGISTER
WDCON (A7H)
PRE2
PRE1
PRE0
-
-
WDRUN
WDTOF
WDCLK
002aaa905
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence.
Fig 23. Watchdog timer in Watchdog mode (WDTE = `1')
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8.26 Additional features
8.26.1 Software reset
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. Care should be taken when writing to AUXR1 to avoid accidental software resets.
8.26.2 Dual data pointers
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.
8.27 Flash program memory
8.27.1 General description
The P89LPC912/913/914 flash memory provides in-circuit electrical erasure and programming. The flash can be erased, read, and written as bytes. The Sector and Page Erase functions can erase any flash sector (256 B) or page (16 B). The Chip Erase operation will erase the entire program memory. ICP using standard commercial programmers is available. In addition, IAP and byte erase allows code memory to be used for non-volatile data storage. On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC912/913/914 flash reliably stores memory contents even after 400000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. The P89LPC912/913/914 uses VDD as the supply voltage to perform the Program/Erase algorithms.
8.27.2 Features
* * * * * * * *
Programming and erase over the full operating voltage range. Byte erase allows code memory to be used for data storage. Read/Programming/Erase using ICP. Any flash program/erase operation in 2 ms. Programming with industry-standard commercial programmers. Programmable security for the code in the flash for each sector. 400000 typical erase/program cycles for each byte. 20 year minimum data retention.
8.27.3 Flash organization
The P89LPC912/913/914 program memory consists of four 256 byte sectors. Each sector can be further divided into 16 B pages. In addition to sector erase, page erase, and byte erase, a 16 B page register is included which allows from 1 B to 16 B of a given page to be programmed at the same time, substantially reducing overall programming time. In addition, erasing and reprogramming of user-programmable configuration bytes including UCFG1, the Boot Status Bit, and the Boot Vector is supported.
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8.27.4 Flash programming and erasing
Different methods of erasing or programming of the flash are available. The flash may be programmed or erased in the end-user application (IAP-Lite) under control of the application's firmware. Another option is to use the ICP mechanism. This ICP system provides for programming through a serial clock- serial data interface using a commercially available EPROM programmer which supports this device. This device does not provide for direct verification of code memory contents. Instead, this device provides a 32-bit CRC result on either a sector or the entire 1 kB of user code space.
8.27.5 In-circuit programming
ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC912/913/914 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application, using commercially available programmers, possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins. Only a small connector (with VDD, VSS, RST, clock, and data signals) needs to be available to interface your application to a commercial programmer in order to use this feature. Additional details may be found in the P89LPC912/913/914 User manual.
8.27.6 In-application programming (IAP-Lite)
In-Application Programming is performed in the application under the control of the microcontroller's firmware. The IAP-Lite facility consists of internal hardware resources to facilitate programming and erasing. The NXP In-Application Programming Lite has made in-application programming in an embedded application possible without additional components. This is accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC912/913/914 User manual.
8.27.7 Using flash as data storage
The flash code memory array of this device supports individual byte erasing and programming. Any byte in the code memory array may be read using the MOVC instruction, provided that the sector containing the byte has not been secured (a MOVC instruction is not allowed to read code memory contents of a secured sector). Thus any byte in a non-secured sector may be used for non-volatile data storage.
8.27.8 User configuration bytes
Some user-configurable features of the P89LPC912/913/914 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1. Please see the P89LPC912/913/914 User manual for additional details.
8.27.9 User sector security bytes
There are four User Sector Security Bytes, each corresponding to one sector. Please see the P89LPC912/913/914 User manual for additional details.
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9. Limiting values
Table 12. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Tamb(bias) Tstg IOH(I/O) IOL(I/O) II/Otot(max) Vn Ptot(pack) Parameter bias ambient temperature storage temperature HIGH-level output current per input/output pin LOW-level output current per input/output pin maximum total input/output current voltage on any other pin total power dissipation (per package) except VSS, with respect to VDD based on package heat transfer, not device power consumption Conditions Min -55 -65 -0.5 Max +125 +150 8 20 120 +5.5 1.5 Unit C C mA mA mA V W
[1]
The following applies to Table 12 "Limiting values": a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
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10. Static characteristics
Table 13. Static characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, -40 C to +125 C for extended, unless otherwise specified. Symbol IDD(oper) Parameter operating supply current P89LPC912, P89LPC913 VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz P89LPC914 IDD(idle) Idle mode supply current P89LPC912, P89LPC913 VDD = 3.6 V; fosc = 12 MHz VDD = 3.6 V; fosc = 18 MHz P89LPC914 IDD(pd) IDD(tpd) (dV/dt)r (dV/dt)f VDDR Vth(HL) Vth(LH) Vhys VOL Power-down mode supply current total Power-down mode supply current rise rate fall rate data retention supply voltage HIGH-LOW threshold voltage LOW-HIGH threshold voltage hysteresis voltage LOW-level output voltage IOL = 20 mA; all ports IOL = 10 mA; all ports IOL = 3.2 mA; all ports VOH HIGH-level output voltage IOH = -8 mA; all ports, push-pull mode IOH = -3.2 mA; all ports, push-pull mode IOH = -20 A; all ports, quasi-bidirectional mode Ciss IIL ILI ITHL input capacitance LOW-state input current input leakage current HIGH-LOW transition current VI = 0.4 V; all ports VI = VIL or VIH; all ports VI = 2.0 V at VDD = 3.6 V; all ports
[4] [5] [6] [7][8] [2] [2]
Conditions
Min -
Typ[1] 7 11 4
Max 13 16 8
Unit mA mA mA
[2]
VDD = 3.6 V; fosc = 7.373 MHz
[3]
1.5 0.22VDD VDD - 1.0 VDD - 0.7 VDD - 0.3 -30 10
1.5 4 1 0.5 0.4VDD 0.6VDD 0.2VDD 0.6 0.3 0.2 VDD - 0.4 VDD - 0.2 -
5.6 6 3 70 5 2 50 0.7VDD 1.0 0.5 0.3 15 -80 1 -450 30
mA mA mA A A mV/s mV/s V V V V V V V V V V pF A A A k
[2]
VDD = 3.6 V; fosc = 7.373 MHz VDD = 3.6 V VDD = 3.6 V of VDD of VDD except SCL, SDA except SCL, SDA
[3]
[2][3]
[2][3]
RRST_N(int) internal pull-up resistance on pin RST
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Table 13. Static characteristics ...continued VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, -40 C to +125 C for extended, unless otherwise specified. Symbol Vbo Vref(bg) TCbg Parameter brownout trip voltage band gap reference voltage band gap temperature coefficient Conditions 2.4 V < VDD < 3.6 V; with BOV = 1, BOPD = 0 Min 2.40 1.19 Typ[1] 1.23 10 Max 2.70 1.27 20 Unit V V ppm/ C
[1] [2] [3] [4] [5] [6] [7] [8]
Typical ratings are not guaranteed. The values listed are at room temperature, VDD = 3 V. The IDD(oper), IDD(idle) and IDD(pd) specifications are measured using an external clock with the following functions disabled: comparators, brownout detect, and watchdog timer (P89LPC912, P89LPC913). The IDD(oper), IDD(idle) and IDD(pd) specifications are measured with the following functions disabled: comparators, brownout detect, and watchdog timer (P89LPC914). Pin capacitance is characterized but not tested. Measured with port in quasi-bidirectional mode. Measured with port in high-impedance mode. Ports in quasi-bidirectional mode with weak pull-up (applies to all port pins with pull-ups) Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when VI is approximately 2 V.
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11. Dynamic characteristics
Table 14. Dynamic characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, -40 C to +125 C for extended, unless otherwise specified.[1] Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions nominal f = 7.3728 MHz; trimmed to 1 % at Tamb = 25 C nominal f = 400 kHz Variable clock Min 7.189 Max 7.557 fosc = 12 MHz Min 7.189 Max 7.557 MHz Unit
fosc(WD)
internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency glitch rejection
320
520
320
520
kHz
Crystal oscillator (P89LPC912, P89LPC913) fosc Tcy(clk) fCLKLP Glitch filter tgr P1.5/RST pin any pin except P1.5/RST tsa signal acceptance P1.5/RST pin any pin except P1.5/RST External clock (P89LPC912, P89LPC913) tCHCX tCLCX tCLCH tCHCL TXLXL tQVXH tXHQX tXHDX tXHDV clock HIGH time clock LOW time clock rise time clock fall time serial port clock cycle time see Figure 25 see Figure 25 see Figure 25 see Figure 25 see Figure 24 33 33 16Tcy(clk) 13Tcy(clk) 150 Tcy(clk) - tCLCX Tcy(clk) - tCHCX 8 8 Tcy(clk) + 20 0 33 33 1333 1083 150 8 8 103 0 ns ns ns ns ns ns ns ns ns 125 50 50 15 125 50 50 15 ns ns ns ns 0 see Figure 25 83 0 12 8 MHz ns MHz
Shift register (UART mode 0 - P89LPC913, P89LPC914) output data set-up to clock rising see Figure 24 edge output data hold after clock rising see Figure 24 edge input data hold after clock rising edge input data valid to clock rising edge SPI operating frequency 2.0 MHz (slave) 3.0 MHz (master) TSPICYC SPI cycle time slave master
P89LPC912_913_914_5
see Figure 24 see Figure 24
SPI interface fSPI 0 see Figure 26, 27, 28, 29
6 CCLK 4 CCLK CCLK 6 CCLK 4
0 500 333
2.0 3.0 -
MHz MHz ns ns
-
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Table 14. Dynamic characteristics ...continued VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, -40 C to +125 C for extended, unless otherwise specified.[1] Symbol tSPILEAD tSPILAG tSPICLKH Parameter SPI enable lead time slave SPI enable lag time slave SPICLK HIGH time master slave tSPICLKL SPICLK LOW time master slave tSPIDSU tSPIDH tSPIA SPI data set-up time SPI data hold time SPI access time slave tSPIDIS SPI disable time slave tSPIDV SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) tSPIF SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1]
Conditions see Figure 28, 29 see Figure 28, 29 see Figure 26, 27, 28, 29
Variable clock Min 250 250
2 CCLK 3 CCLK
fosc = 12 MHz Min 250 250 165 250 165 250 100 100 Max -
Unit
Max -
ns ns ns ns ns ns ns ns
see Figure 26, 27, 28, 29
2 CCLK 3 CCLK
see Figure 26, 27, 28, 29 see Figure 26, 27, 28, 29 see Figure 28, 29 see Figure 28, 29
100 100
0
120
0
120
ns
0 see Figure 26, 27, 28, 29 see Figure 26, 27, 28, 29 see Figure 26, 27, 28, 29 0
240
-
240
ns
240 167 -
0
240 167 -
ns ns ns
-
100 2000
-
100 2000
ns ns
see Figure 26, 27, 28, 29
-
100 2000
-
100 2000
ns ns
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
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8-bit microcontrollers with two-clock 80C51 core
Table 15. Dynamic characteristics (P89LPC912, P89LPC913) VDD = 3.0 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, -40 C to +125 C for extended, unless otherwise specified.[1] Symbol fosc(RC) Parameter Conditions Variable clock Min internal RC oscillator frequency nominal f = 7.3728 MHz trimmed to 1 % at Tamb = 25 C internal watchdog oscillator frequency oscillator frequency clock cycle time low-power select clock frequency glitch rejection P1.5/RST pin any pin except P1.5/RST tsa signal acceptance P1.5/RST pin any pin except P1.5/RST External clock tCHCX tCLCX tCLCH tCHCL fSPI clock HIGH time clock LOW time clock rise time clock fall time SPI operating frequency 3.0 MHz (slave) 4.5 MHz (master) TSPICYC SPI cycle time slave master see Figure 26, 27, 28, 29
6 4 CCLK CCLK
fosc = 18 MHz Min 7.189 Max 7.557
Unit MHz
Max 7.557
7.189
fosc(WD)
nominal f = 400 kHz
[2]
320
520
320
520
kHz
Crystal oscillator fosc Tcy(clk) fCLKLP 0 55 0 18 8 MHz ns MHz see Figure 25
Glitch filter tgr 125 50 50 15 125 50 50 15 ns ns ns ns
see Figure 25 see Figure 25 see Figure 25 see Figure 25
22 22 -
Tcy(clk) - tCLCX Tcy(clk) - tCHCX 5 5
22 22 -
5 5
ns ns ns ns
SPI interface 0 CCLK CCLK
6 4
0 -
3 4.5
MHz MHz
-
333 222
-
ns ns
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8-bit microcontrollers with two-clock 80C51 core
Table 15. Dynamic characteristics (P89LPC912, P89LPC913) ...continued VDD = 3.0 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, -40 C to +125 C for extended, unless otherwise specified.[1] Symbol tSPILEAD Parameter SPI enable lead time slave tSPILAG SPI enable lag time slave tSPICLKH SPICLK HIGH time master slave tSPICLKL SPICLK LOW time master slave tSPIDSU tSPIDH tSPIA SPI data set-up time SPI data hold time SPI access time slave tSPIDIS SPI disable time slave tSPIDV SPI enable to output data valid time slave master tSPIOH tSPIR SPI output data hold time SPI rise time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS) see Figure 26, 27, 28, 29 see Figure 26, 27, 28, 29 100 2000 100 2000 ns ns see Figure 26, 27, 28, 29 0 0 0 160 111 0 160 111 ns ns ns see Figure 28, 29 see Figure 28, 29 0 160 160 ns 0 80 0 80 ns see Figure 26, 27, 28, 29 see Figure 26, 27, 28, 29 see Figure 26, 27, 28, 29
2 3 CCLK CCLK
Conditions see Figure 28, 29
Variable clock Min Max
fosc = 18 MHz Min Max
Unit
250 see Figure 28, 29 250 see Figure 26, 27, 28, 29
2 3 CCLK CCLK
-
250
-
ns
-
250
-
ns
-
111 167
-
ns ns
-
111 167 100 100
-
ns ns ns ns
100 100
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
Table 15. Dynamic characteristics (P89LPC912, P89LPC913) ...continued VDD = 3.0 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, -40 C to +125 C for extended, unless otherwise specified.[1] Symbol tSPIF Parameter SPI fall time SPI outputs (SPICLK, MOSI, MISO) SPI inputs (SPICLK, MOSI, MISO, SS)
[1] [2]
Conditions see Figure 26, 27, 28, 29 -
Variable clock Min Max
fosc = 18 MHz Min Max
Unit
100 2000
-
100 2000
ns ns
Parameters are valid over operating temperature range unless otherwise specified. Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz. When using an oscillator frequency above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit is required to hold the device in reset at power-up until VDD has reached its specified level. When system power is removed VDD will fall below the minimum specified operating voltage. When using an oscillator frequency above 12 MHz, in some applications, an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage.
11.1 Waveforms
TXLXL clock tQVXH output data 0 write to SBUF input data clear RI set RI
002aaa906
tXHQX 1 tXHDX 2 3 4 5 6 7
tXHDV
valid valid valid valid valid valid valid
set TI
valid
Fig 24. Shift register mode timing
VDD - 0.5 V 0.45 V
0.2VDD + 0.9 V 0.2VDD - 0.1 V tCHCL tCLCX Tcy(clk)
002aaa907
tCHCX tCLCH
Fig 25. External clock timing
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8-bit microcontrollers with two-clock 80C51 core
SS TSPICYC tSPIF tSPICLKH SPICLK (CPOL = 0) (output) tSPIF tSPICLKL tSPIR tSPICLKH SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIR tSPICLKL tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF master MSB/LSB out master LSB/MSB out
002aaa908
Fig 26. SPI master timing (CPHA = 0)
SS TSPICYC tSPIF tSPICLKL tSPIR tSPICLKH
SPICLK (CPOL = 0) (output) tSPIF SPICLK (CPOL = 1) (output) tSPICLKH tSPICLKL tSPIR
tSPIDSU MISO (input)
tSPIDH LSB/MSB in tSPIOH tSPIDV tSPIDV tSPIR
MSB/LSB in tSPIDV
MOSI (output)
tSPIF master MSB/LSB out master LSB/MSB out
002aaa909
Fig 27. SPI master timing (CPHA = 1)
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NXP Semiconductors
P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
SS
tSPIR tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIA tSPIOH tSPIDV MISO (output) tSPIF
TSPICYC tSPICLKH tSPICLKL tSPIR tSPILAG
tSPIR
tSPICLKL
tSPIR tSPICLKH
tSPIOH tSPIDV
tSPIOH
tSPIDIS
slave MSB/LSB out
slave LSB/MSB out
not defined
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa910
Fig 28. SPI slave timing (CPHA = 0)
SS tSPIR tSPILEAD SPICLK (CPOL = 0) (input) tSPIF SPICLK (CPOL = 1) (input) tSPIOH tSPIDV tSPIA MISO (output) not defined slave MSB/LSB out slave LSB/MSB out tSPICLKL tSPIR tSPICLKH tSPIF tSPICLKH tSPIR tSPIR tSPILAG
TSPICYC tSPICLKL
tSPIOH tSPIDV
tSPIOH tSPIDV tSPIDIS
tSPIDSU MOSI (input)
tSPIDH
tSPIDSU
tSPIDSU
tSPIDH
MSB/LSB in
LSB/MSB in
002aaa911
Fig 29. SPI slave timing (CPHA = 1)
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Product data sheet
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8-bit microcontrollers with two-clock 80C51 core
12. Other characteristics
12.1 Comparator electrical characteristics
Table 16. Comparator electrical characteristics VDD = 2.4 V to 3.6 V, unless otherwise specified. Tamb = -40 C to +85 C for industrial, -40 C to +125 C for extended, unless otherwise specified. Symbol VIO VIC CMRR tres(tot) t(CE-OV) ILI
[1]
Parameter input offset voltage common-mode input voltage common-mode rejection ratio total response time chip enable to output valid time input leakage current
Conditions
Min 0
[1]
Typ 250 -
Max 10 VDD - 0.3 -50 500 10 1
Unit mV V dB ns s A
-
0 V < VI < VDD
-
This parameter is characterized, but not tested in production.
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8-bit microcontrollers with two-clock 80C51 core
13. Package outline
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
D
E
A
X
c y HE vMA
Z
14
8
Q A2 pin 1 index A1 Lp L (A 3) A
1
e bp
7
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 o 0
o
Fig 30. Package outline SOT402-1 (TSSOP14)
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8-bit microcontrollers with two-clock 80C51 core
14. Abbreviations
Table 17. Acronym CRC EPROM EMI ISP LSB MSB PWM RC RTC SFR SPI UART Acronym list Description Cyclic Redundancy Check Erasable Programmable Read-Only Memory ElectroMagnetic Interference In-System Programming Least Significant Bit Most Significant Bit Pulse Width Modulator Resistance-Capacitance Real-Time Clock Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter
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8-bit microcontrollers with two-clock 80C51 core
15. Revision history
Table 18. Revision history Release date 20070928 Data sheet status Product data sheet Product data sheet Change notice Supersedes P89LPC912_913_914_4 P89LPC912_913_914-03 Document ID P89LPC912_913_914_5 Modifications: P89LPC912_913_914_4 Modifications:
* * * *
Figure 10, 11 and 12: changed incorrect character font The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added P89LPC912HDH Product data Product data Objective data 01-A14930 P89LPC912_913_914-02 P89LPC912_913_914-01 -
20070830
P89LPC912_913_914-03 20041217 P89LPC912_913_914-02 20031212 P89LPC912_913_914-01 20030711
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8-bit microcontrollers with two-clock 80C51 core
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
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Product data sheet
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P89LPC912/913/914
8-bit microcontrollers with two-clock 80C51 core
18. Contents
1 2 2.1 2.2 3 4 4.1 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.11.1 8.12 8.12.1 8.12.2 8.12.3 8.12.4 8.12.5 8.12.6 8.12.7 8.13 8.13.1 8.13.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 Product comparison . . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 9 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional description . . . . . . . . . . . . . . . . . . 16 Special function registers . . . . . . . . . . . . . . . . 16 Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 28 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 28 CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 28 Low-speed oscillator option (P89LPC912, P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Medium-speed oscillator option (P89LPC912, P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 High-speed oscillator option (P89LPC912, P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Clock output (P89LPC912, P89LPC913) . . . . 29 On-chip RC oscillator option . . . . . . . . . . . . . . 29 Watchdog oscillator option . . . . . . . . . . . . . . . 29 External clock input option (P89LPC912, P89LPC913) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 31 CCLK modification: DIVM register . . . . . . . . . 31 Low power select . . . . . . . . . . . . . . . . . . . . . . 31 Memory organization . . . . . . . . . . . . . . . . . . . 31 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 External interrupt inputs . . . . . . . . . . . . . . . . . 32 I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Port configurations . . . . . . . . . . . . . . . . . . . . . 34 Quasi-bidirectional output configuration . . . . . 34 Open-drain output configuration . . . . . . . . . . . 35 Input-only configuration . . . . . . . . . . . . . . . . . 35 Push-pull output configuration . . . . . . . . . . . . 35 Port 0 analog functions . . . . . . . . . . . . . . . . . . 35 Additional port features. . . . . . . . . . . . . . . . . . 36 Power monitoring functions. . . . . . . . . . . . . . . 36 Brownout detection . . . . . . . . . . . . . . . . . . . . . 36 Power-on detection . . . . . . . . . . . . . . . . . . . . . 36 8.14 8.14.1 8.14.2 8.14.3 8.15 8.16 8.16.1 8.16.2 8.16.3 8.16.4 8.16.5 8.16.6 8.17 8.18 8.18.1 8.18.2 8.18.3 8.18.4 8.18.5 8.18.6 8.18.7 8.18.8 8.18.9 8.18.10 8.19 8.19.1 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.26.1 8.26.2 8.27 8.27.1 8.27.2 8.27.3 8.27.4 8.27.5 8.27.6 8.27.7 8.27.8 8.27.9 Power reduction modes . . . . . . . . . . . . . . . . . Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-down mode . . . . . . . . . . . . . . . . . . . . . Total Power-down mode . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timers/counters 0 and 1 . . . . . . . . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 6 (P89LPC912, P89LPC914) . . . . . . . . Timer overflow toggle output (P89LPC912, P89LPC914). . . . . . . . . . . . . . . . . . . . . . . . . . RTC/system timer. . . . . . . . . . . . . . . . . . . . . . UART (P89LPC913, P89LPC914) . . . . . . . . . Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud rate generator and selection . . . . . . . . . Framing error . . . . . . . . . . . . . . . . . . . . . . . . . Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . Double buffering . . . . . . . . . . . . . . . . . . . . . . . Transmit interrupts with double buffering enabled (modes 1, 2 and 3) . . . . . . The 9th bit (bit 8) in double buffering (modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . Serial Peripheral Interface (SPI). . . . . . . . . . . Typical SPI configurations . . . . . . . . . . . . . . . Analog comparators . . . . . . . . . . . . . . . . . . . . Internal reference voltage. . . . . . . . . . . . . . . . Comparator interrupt . . . . . . . . . . . . . . . . . . . Comparators and power reduction modes . . . Keypad interrupt . . . . . . . . . . . . . . . . . . . . . . . Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . Additional features . . . . . . . . . . . . . . . . . . . . . Software reset . . . . . . . . . . . . . . . . . . . . . . . . Dual data pointers . . . . . . . . . . . . . . . . . . . . . Flash program memory . . . . . . . . . . . . . . . . . General description . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash organization . . . . . . . . . . . . . . . . . . . . . Flash programming and erasing. . . . . . . . . . . In-circuit programming . . . . . . . . . . . . . . . . . . In-application programming (IAP-Lite) . . . . . . Using flash as data storage . . . . . . . . . . . . . . User configuration bytes. . . . . . . . . . . . . . . . . User sector security bytes . . . . . . . . . . . . . . . 36 37 37 37 37 38 38 38 38 39 39 39 39 39 39 40 40 40 40 40 41 41 41 41 41 43 45 45 45 46 46 47 48 48 48 48 48 48 48 49 49 49 49 49 49
continued >>
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NXP Semiconductors
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8-bit microcontrollers with two-clock 80C51 core
50 51 53 57 60 60 61 62 63 64 64 64 64 64 64 65
9 10 11 11.1 12 12.1 13 14 15 16 16.1 16.2 16.3 16.4 17 18
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics. . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . Other characteristics . . . . . . . . . . . . . . . . . . . . Comparator electrical characteristics . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 28 September 2007 Document identifier: P89LPC912_913_914_5

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